1. Field of the Invention
The present invention relates to an output stage. More particularly, the present invention relates to a low voltage differential signal output stage.
2. Description of Related Art
FIG. 1 is a block diagram illustrating a conventional low voltage differential signal (LVDS) output stage. Referring to FIG. 1, the LVDS output stage 100 includes a display signal digital circuit 110, a display phase-locked loop (PLL) 120, a data parallel to serial (P2S) circuit 130 and a LVDS transmitting circuit 140.
The display PLL 120 locks a phase of a multiply-by-1 frequency multiplication display clock signal 112 transmitted from the display signal digital circuit 110, and multiplies the frequency by 7 to generate a multiply-by-7 frequency multiplication display clock signal 122. Thereafter, the data P2S circuit 130 simultaneously receives the multiply-by-1 frequency multiplication display clock signal 112, the multiply-by-7 frequency multiplication display clock signal 122 and display digital data (for example, a horizontal sync signal hs, a vertical sync signal vs, a data enable signal de, and a three basic color signal rgb), and performs a P2S operation to the display digital data hs, vs, de and rgb. Then, the serialized display digital data hs, vs, de and rgb are transmitted to the LVDS transmitting circuit 140 to achieve a high speed LVDS format transmission.
FIG. 2 is a block diagram illustrating the data P2S circuit 130 of FIG. 1. Referring to FIG. 2, a fixed value frequency divider 210 (divided-by-7) divides the multiply-by-7 frequency multiplication display clock signal 122 by 7, and generates a multiply-by-1 frequency multiplication transmission clock signal 212. Then, the transmission clock signal 212 is transmitted to the LVDS transmitting circuit 140 to serve as an output of a final clock signal. Moreover, during a dividing process of the fixed value frequency divider 210, the fixed value frequency divider 210 generates a load signal ld according to the display clock signal 112. The load signal ld is generated every 7 clock cycles of the multiply-by-7 frequency multiplication display clock signal 122, and triggers the data P2S circuit 220 to serialize the display digital data hs, vs, de and rgb to generate a serial data signal 222 (a display data signal output with a multiply-by-7 frequency multiplication). Then, the serial data signal 222 is output to the LVDS transmitting circuit 140 to complete the whole conversion operation of P2S.
Referring to FIG. 1 and FIG. 2 again, in a structure of the LVDS output stage 100, there is a phase locking relationship between the multiply-by-7 frequency multiplication display clock signal 122 and the multiply-by-1 frequency multiplication display clock signal 112, and there is a sync relationship between the display digital data hs, vs, de, rgb and the multiply-by-1 frequency multiplication display clock signal 112. Therefore, the data P2S circuit 220 can securely complete the data P2S operation by only referring to the multiply-by-1 frequency multiplication display clock signal 112 and selecting a suitable load signal ld.
In addition, the display PLL 120 is a conventional PLL, and a design thereof is more complicated than a frequency synthesizer, and limitations of the display PLL 120 are relatively more. Moreover, to ensure an output signal of the LVDS output stage 100 achieving a function of reducing a system electromagnetic interference (EMI), the display PLL 120 is generally required to have a spread spectrum output function. According to the conventional method, if the display PLL 120 has the spread spectrum output function, two PLLs are generally required to be connected in serial, which may increase a cost of the circuit, and the whole circuit structure is complicated and is lack of flexibility.